In a prior art integrated semiconductor device having multiple conducting layers it has been difficult to establish proper wiring between target conducting layers. For example, with a high-resistance load type SRAM, resistance elements and power supply lines are made of polycrystalline silicon films within a memory cell array and are wired through contact holes at the boundary of the array with electric wire parts made of metal films such as aluminum films located outside the memory cell array.
However, this type of SRAM has been defective in that, when the polycrystalline silicon film is made thin for the purpose of obtaining a high resistance, the contact holes may often be made penetrating the film, which results in short-circuiting between the power supply and grounding lines where the contact holes are formed on the grounding lines.
FIG. 7 shows an equivalent circuit of an exemplary high-resistance, 4-transistor cell of an SRAM. This memory cell 11 has a flip-flop 12 which comprises a pair of inverters 13 and 14 having inputs and outputs wired in cross connection. The inverters 13 and 14 are made up of driver transistors 15, 16 and load resistor elements 17, 18 respectively. Additional transferring transistors 21 and 22 form the memory cell 11 together with the above flip-flop 12.
The transistors 15 and 16 are connected at their sources to a common grounding line 23, while the resistor elements 17 and 18 are connected to a common power supply line 24. The transistors 21 and 22 are connected at their gates to a common word line 25, and also connected at ones of their sources and drains to bit lines 26 and 17.
The resistor elements 17 and 18 are generally made of a high-resistance polycrystalline silicon film, and the power supply line 24 within the memory cell array is made by lowering the resistance of the corresponding part of the same polycrystalline silicon film as the resistor elements 17 and 18. For the purpose of minimizing the standby current of the cell array and thereby reducing its power consumption by increasing the resistance values of the resistor elements 17 and 18, it is common practice to make thin the polycrystalline silicon film of the resistor elements 17 and 18 as about 50 nm.
As further shown in FIG. 8, the power supply line 24 usually has a power supply line part 24a made of a polycrystalline silicon film within the memory cell array and also has another power supply line part 24b made of a metallic film as an aluminum film outside the memory cell array. Therefore, as shown in FIGS. 8 and 9, these power supply line parts 24a and 24b are contacted with each other through a contact hole 31, at the boundary between the outside and inside of the memory cell array.
With the SRAM having an arrangement as mentioned above, usually, the gate electrodes of the transistors 13 and 14 and the word line 25 are made of a polycrystalline silicon film as the first layer, the grounding line 23 is made of a polycrystalline silicon as the second layer, and the resistor elements 17 and 18 and the power supply line part 24a are made of a polycrystalline silicon film as the third layer on a semiconductor substrate.
Furthermore, for the purpose of decreasing the area of the memory cell to thereby increase its integration density, in one method, the contact hole 31 between the power supply line parts 24a as the third layer and the power supply line parts 24b is made immediately above the grounding line 23 of the polycrystalline silicon film of the second layer as shown in FIG. 8.
As already mentioned above, the polycrystalline silicon film of the third layer is about 50 nm thin. The contact hole 31 is made by etching an interlayer insulating film (made of SiO.sub.2 in most cases) disposed between the power supply line parts 24a and 24b to electrically connect the line parts 24a and 24b as shown in FIG. 9. However, when the contact hole 31 is made, the polycrystalline silicon film of the power supply line part 24a may fail to function as an etching stopper, with the result that the contact hole 31 undesirably penetrates even the power supply line part 24a.
In addition, since the interlayer insulating film 33 between the power supply line part 24a and grounding line 23 is usually made of an SiO.sub.2 film, when the contact hole 31 is made through the power supply line part 24a, the contact hole 31 is also extended through the interlayer insulating film 33 and often reaches even the grounding line 23, as shown by dotted lines in FIG. 9.
Under such a condition, when the power supply line part 24b is formed, this causes the power supply line part 24b to be contacted even with the grounding line 23 through the contact hole 31, thus disadvantageously resulting in that short-circuiting takes place between the power supply and grounding lines 24 and 23.
In order to eliminate such a disadvantage, such a highly difficult technology is required to control the etching process to prevent the contact hole 31 from reaching the grounding line 23.